“With our IBIS5.0 modeling technique and the HyperLynx power-aware SI solution, we achieved a 95 percent reduction in simulation time with excellent correlation to transistor-level simulation. Socionext is working with its customers and partners to address this challenge, and we collaborated with Mentor Graphics to develop a HyperLynx DDR4 simulation kit,” stated Takayuki Tsuru, director of the custom SoC Business Unit, SoC Product Solution Department, Socionext.

Over 2Gbps, SSN (Simultaneous Switching Noise) must be considered when designing and simulating DDR4 circuits. “Socionext is addressing SI/PI issues that get more complicated at higher frequencies. New features in the HyperLynx SI/PI product include power-aware IBIS model support and the DDRx wizard for DDR4/LPDDR4 (next-generation memory for low-power design) validation. The comprehensive HyperLynx SI/PI product provides tools for pre- and post-layout signal integrity, timing, crosstalk and power integrity analysis to quickly generate accurate simulation results to prevent design re-spins. With the increased complexity and high-speed performance of today’s integrated circuits (ICs), a growing number of PCBs suffer from signal degradation and timing problems which are exacerbated by power delivery issues this impacts board performance and possibly total failed logic, requiring costly redesign. The HyperLynx product addresses high-speed systems design problems throughout the design flow-starting at the earliest architectural stages through post-layout verification. Mentor Graphics has announced its newest version of the HyperLynx Signal Integrity/Power Integrity (SI/PI) product for high-speed printed circuit board (PCB) designs.

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